WdgRV: RISC-V watchdog IP headed for open silicon



HeiChips has been submitted to fabrication—and that is worth a short announcement.
The group at the University of Heidelberg integrated all the designs of the hackathon from HeiChips 2026 into a 9 mm² open-source chip. The tapeout was done in the IHP’s SG13CMOS shuttle. Featuring: 14 user projects from the HeiChips Summer School 2025, including two RISC-V cores, mixed-signal designs, and a reprogrammable FPGA fabric that routes projects to I/O and SRAM via Yosys/nextpnr bitstreams. The ASIC flow runs on LibreLane 3.0—tapeout-ready from a single command. Open silicon is starting to feel routine in the best way.
I contributed WdgRV in that context: a RISC-V watchdog peripheral with a Wishbone interface, aligned with the community watchdog spec. It is the kind of small, reusable block that belongs next to student SoCs on a shuttle like this—not a full chip by itself, but a standard piece of recovery logic for when firmware stops kicking the dog. I used the amazing Rggen framework to generate the wishbone register interface used by the IP.
The integration story ties directly to HeiChips. Meinhard Kissich’s recap of #HeiChips2025 captures the hackathon side: an SoC built around the bit-serial FazyRV core, a custom instruction interface, and a team (Spandan Das, Marcin Kowalczyk, Matthias Musch, Muhammad Sabih) that took the hackathon award alongside the CORDIC group—then pushed toward verification and tapeout on IHP SG13G2. WdgRV is documented with FazyRV as the reference integration (reset- or interrupt-based recovery). Credit to Meinhard and that team for the SoC context; credit to Leo and everyone behind HeiChips for making the shuttle real.
Repo: github.com/matztron/WdgRV (MIT)
Credits
- HeiChips tapeout & summer school: Leo Moser and NCT Team of University of Heidelberg
- FazyRV SoC & HeiChips2025: Meinhard Kissich
- RISC-V Watchdog spec: riscvarchive/riscv-watchdog
If you are wiring up a RISC-V block for open silicon, take a look—and tell me how it goes on real silicon.